1. Field
Example embodiments relate to memory devices and methods of manufacturing the same. Example embodiments may relate, for example, to memory devices having improved integration and methods of manufacturing the same.
2. Description of the Related Art
Semiconductor memory devices may be classified into volatile memory devices such as dynamic random access memory (DRAM) devices or static random access memory (SRAM) devices, in which input/output operations of data may be performed relatively fast but data may be lost as time elapses, and non-volatile memory devices such as read only memory (ROM) devices, in which input/output operations of data may be performed relatively slow but data may be permanently stored.
Recently, demand for electrically erasable programmable read only memory (EEPROM) devices or flash memory devices, which are types of non-volatile memory devices, have increased. Flash memory devices may electrically perform programming and erasing operations using a Fowler-Nordheim (FN) tunneling and/or channel hot electron injection (CHEI) methods. The flash memory devices may be classified into floating gate type memory devices and floating trap type memory devices such as silicon-oxide-nitride-oxide-silicon (SONOS) devices or metal-oxide-nitride-oxide-semiconductor (MONOS) devices.
The floating trap type memory device may include a charge trapping layer and a gate electrode on a semiconductor substrate. The charge trapping layer may have a tunnel insulation layer, a charge storing layer that stores charges moving through a channel region, and/or a blocking layer on the semiconductor substrate.
A unit cell of the floating trap type memory device may serve as a single-level cell (SLC) or a multi-level cell (MLC). If the unit cell of the floating trap type memory device serves as an SLC, a logic value of “0” or “1” may be stored in a charge trapping layer, whereas if the unit cell of the floating trap type memory device serves as an MLC, a logic value of “00,” “01,” “10,” or “11” may be stored in the charge trapping layer.
Recently, attempts have been made to comply with demand for increased integration of semiconductor memory devices. However, conventional methods to increase integration of semiconductor memory devices by decreasing the size of unit members of the semiconductor memory devices (hereinafter “scale-down methods”) have been difficult due to technical limits of performing a photolithographical process and degradation of the unit members generated by a short channel effect. Although methods of increasing integration outside of decreasing the size of the unit members have been studied, integration of the semiconductor memory devices has not been sufficient and remains an essential subject for development.